FlyDSL Documentation

FlyDSL is a Python DSL and MLIR compiler stack for authoring high-performance GPU kernels with explicit layout algebra, targeting AMD ROCm/HIP GPUs.

FlyDSL is the Python front-end (Flexible Layout Python DSL) powered by the Fly dialect: an MLIR-native compiler stack with first-class layout IR (!fly.int_tuple, !fly.layout, !fly.coord_tensor, !fly.memref), explicit algebra and coordinate mapping, plus a composable lowering pipeline to GPU/ROCDL.

Getting Started

• Installation
  • Prerequisites
  • Install from PyPI
  • Build from source
  • Verify Installation
  • Troubleshooting
• Quick Start
  • A Minimal Vector Add Kernel
  • Key Concepts
  • Compilation Pipeline
  • AOT Pre-compilation
  • Next Steps

Language Specification

• Arithmetic Types
  • The type tower
  • Compile-time and run-time values
  • Type interoperability

Guides

• Architecture & Compilation Pipeline Guide
  • Quick Reference
  • 1. Project Structure
  • 2. Architecture
  • 3. Compilation Pipeline
  • 4. Key Abstractions
  • 5. Environment Variables
  • 6. Target Hardware
  • 7. IR Dump Workflow
  • 8. Source Files
• Layout Algebra Guide
  • Quick Reference
  • 1. Core Types
  • 2. Construction
  • 3. Coordinate Mapping
  • 4. Query Operations
  • 5. Layout Algebra
  • 6. Product Operations
  • 7. Divide Operations
  • 8. Structural Operations
  • 9. MemRef / View / Copy Operations
  • 10. Nested / Hierarchical Layouts
  • 11. IntTuple Arithmetic
  • 12. Printf Debugging
  • 13. Decision Tree
  • 14. Source Files
• Kernel Authoring Guide
  • Quick Reference
  • 1. Basic Kernel Pattern
  • 2. Parameter Types
  • 3. Thread / Block Hierarchy
  • 4. Expression API (flydsl.expr)
  • 5. Control Flow
  • 6. Shared Memory (LDS)
  • 7. Launch Configuration
  • 8. Synchronization
  • 9. Compilation & Caching
  • 10. Debugging
  • 11. Complete Example: Preshuffle GEMM
  • 12. Decision Tree
  • 13. Source Files
• Kernel Tuning Guide
  • 0. Background: The GPU Performance Model
  • 1. Tiling Strategy
  • 2. LDS Double-Buffering (Ping-Pong)
  • 3. LDS Bank-Conflict Swizzle
  • 4. Data Prefetch Pipeline
  • 5. MFMA Instruction Scheduling
  • 6. Epilogue Strategies
  • 7. Register Budget & Occupancy
  • 8. Performance Metrics & Roofline
  • 9. Profiling: ATT Traces & PMC Counters
  • 10. Bisecting a Performance Regression
  • 11. Optimization Checklist
  • See Also
• Pre-built Kernel Library Guide
  • Quick Reference
  • 1. Normalization Kernels
  • 2. Softmax Kernel
  • 3. GEMM Kernel
  • 3b. FlashAttention Forward (kernels/attention/flash_attn_generic.py, kernels/attention/flash_attn_gfx950.py, kernels/attention/flash_attn_fp8_gfx950.py)
  • 4. Shared Utilities
  • 5. Kernel API Comparison
  • 6. Kernel Decision Tree
  • 7. Source Files
  • 8. Test Files
• Testing & Benchmarking Guide
  • Quick Reference
  • 1. Test Categories
  • 2. Test Runner Scripts
  • 3. Pytest Configuration
  • 4. Performance Measurement
  • 5. Test Utilities (tests/utils.py)
  • 6. Writing New Tests
  • 7. GEMM Test CLI Arguments
  • 8. Test Configuration via Environment Variables
  • 9. IR Dump Workflow
  • 10. Source Files
• CuTe Layout Algebra Reference for FlyDSL
  • 1. Overview
  • 2. Layout Algebra Fundamentals
  • 3. FlyDSL Kernel Development
  • 4. Thread and Block Hierarchy
  • 5. Tensor Creation and Memory
  • 6. Data Movement
  • 7. Compute Operations (MFMA)
  • 8. Synchronization
  • 9. Compilation and Execution
  • 10. Complete Example: GEMM with Layout Algebra
  • 11. References

API Reference

• FlyDSL Python DSL
  • Core Module
  • Expression API (flydsl.expr)
  • Compiler API (flydsl.compiler)
• Compiler & Pipeline
  • @flyc.kernel and @flyc.jit
  • Compilation Flow
  • Tensor Arguments
  • Buffer Operations
  • ROCDL Operations
  • fly-opt CLI
• Pre-built Kernels
  • GEMM Kernels
  • MoE (Mixture-of-Experts) Kernels
  • Paged Attention
  • Normalization
  • Softmax
  • Utilities

Tutorials

• Tutorials
  • Basic Usage
  • Kernel Development

Indices and tables

• Index

• Module Index

• Search Page