low.func.def

← low dialect

Target-bound low function definition with register-typed signature values. Without exactness modifiers, registers are virtual and the instruction schedule is free. allocation(...) and schedule(...) are independent contracts: fixed preserves physical register assignment, while locked preserves authored instruction order. schedule(phased) gives each invocation an independent scope whose first phase starts at entry. low.schedule.phase orders successive phases without introducing a new SSA scope or runtime synchronization.

Operation contract

Property	Value
Semantic phase	executable
Traits	SymbolDefine, IsolatedFromAbove
Interfaces	FuncLike

Symbol contract

Property	Value
Kind	function
Defining field	callee
Interfaces	func_like, callable
Flags	—

Signature

Kind	Name	Type	Cardinality	Description
Result	results	register	variadic	—
Attribute	callee	symbol	required	—
Attribute	target	symbol (target)	optional	—
Attribute	descriptor_set	string	required	Canonical descriptor-set key governing the low representation.
Attribute	abi	enum ExportAbiKind	optional	—
Attribute	abi_attrs	dict	optional	—
Attribute	abi_layout	dict	optional	—
Attribute	export_symbol	string	optional	—
Attribute	export_attrs	dict	optional	—
Attribute	visibility	enum Visibility	optional	—
Attribute	cc	enum CallingConv	optional	—
Attribute	purity	enum Purity	optional	—
Attribute	inline_policy	enum InlinePolicy	optional	—
Attribute	allocation	enum LowAllocationMode	optional	—
Attribute	schedule	enum LowScheduleMode	optional	—
Attribute	predicates	predicate_list	optional	—
Attribute	retain	enum Retain	optional	—
Region	body	region	required	Low function body. (terminator low.return.)

Verification constraints

• BlockArgsSatisfy(body)

Examples

low.func.def target<amdgpu.gfx11.generic.core>(@gfx11_generic) @add(%lhs: reg<amdgpu.vgpr x1>, %rhs: reg<amdgpu.vgpr x1>) -> (reg<amdgpu.vgpr x1>) {
  %sum = low.op<amdgpu.v_add_u32>(%lhs, %rhs) : (reg<amdgpu.vgpr x1>, reg<amdgpu.vgpr x1>) -> reg<amdgpu.vgpr x1>
  low.return %sum : reg<amdgpu.vgpr x1>
}

low.func.def target<amdgpu.rdna3_5.core> @invocation_bound() {
  low.return
}

low.func.def schedule(locked) target<amdgpu.gfx11.generic.core>(@gfx11_generic) @exact_order(%lhs: reg<amdgpu.vgpr x1>, %rhs: reg<amdgpu.vgpr x1>) -> (reg<amdgpu.vgpr x1>) {
  %sum = low.op<amdgpu.v_add_u32>(%lhs, %rhs) : (reg<amdgpu.vgpr x1>, reg<amdgpu.vgpr x1>) -> reg<amdgpu.vgpr x1>
  low.return %sum : reg<amdgpu.vgpr x1>
}