vector.atomic.cmpxchg

← vector dialect

Atomic compare-exchange at per-lane signed element offsets. Each lane compares the bits at origin + offsets[lane] with expected[lane], writes replacement[lane] on success, and returns the old memory value. Comparison is bitwise for every accepted element type.

Operation contract

Property	Value
Semantic phase	—
Interfaces	MemoryAccess
Memory effects	readwrite view

Signature

Kind	Name	Type	Cardinality	Description
Operand	expected	vector	required	Expected memory value for each lane.
Operand	replacement	vector	required	Replacement value written for each successful lane.
Operand	view	view	required	Typed destination view.
Operand	offsets	vector	required	Per-lane signed element offsets from the logical origin.
Operand	indices	index	variadic	Dynamic logical origin indices.
Result	old	vector	required	Old memory values read by the atomic operations.
Attribute	success_ordering	enum AtomicOrdering	required	Memory ordering used when a lane compare-exchange succeeds.
Attribute	failure_ordering	enum AtomicOrdering	required	Memory ordering used when a lane compare-exchange fails.
Attribute	scope	enum AtomicScope	required	Required atomic synchronization scope.
Attribute	cache_scope	enum CacheScope	optional	Optional cache/coherency scope required by target lowering.
Attribute	cache_temporal	enum CacheTemporal	optional	Optional temporal cache policy required by target lowering.
Attribute	static_indices	i64_array	required	Static logical origin indices with INT64_MIN sentinels for dynamics.

Verification constraints

• HasBitwiseElement(expected)
• HasIndexOrNonI1IntegerElement(offsets)
• SameElementType(expected, replacement, view, old)
• SameShape(offsets, expected, replacement, old)
• SameType(expected, replacement, old)

Examples

%old = vector.atomic.cmpxchg %expected, %replacement, %view[%row, %col][%offsets] {success_ordering = acq_rel, failure_ordering = acquire, scope = workgroup} : vector<4xi32>, view<[%m]x[%n]xi32, %layout>, vector<4xindex> -> vector<4xi32>