vector.atomic.rmw.mask

← vector dialect

Masked atomic read-modify-write. True mask lanes perform vector.atomic.rmw, while false mask lanes do not access memory and take the corresponding passthrough lane in the result.

Operation contract

Property	Value
Semantic phase	—
Interfaces	MemoryAccess
Memory effects	readwrite view

Signature

Kind	Name	Type	Cardinality	Description
Operand	value	vector	required	Vector update value for each lane.
Operand	view	view	required	Typed destination view.
Operand	offsets	vector	required	Per-lane signed element offsets from the logical origin.
Operand	mask	vector	required	i1 vector mask selecting active atomic lanes.
Operand	passthrough	vector	required	Value used for masked-off result lanes.
Operand	indices	index	variadic	Dynamic logical origin indices.
Result	result	vector	required	Old memory values for active lanes and passthrough for inactive lanes.
Attribute	kind	enum AtomicKind	required	—
Attribute	ordering	enum AtomicOrdering	required	Required atomic memory ordering.
Attribute	scope	enum AtomicScope	required	Required atomic synchronization scope.
Attribute	cache_scope	enum CacheScope	optional	Optional cache/coherency scope required by target lowering.
Attribute	cache_temporal	enum CacheTemporal	optional	Optional temporal cache policy required by target lowering.
Attribute	static_indices	i64_array	required	Static logical origin indices with INT64_MIN sentinels for dynamics.

Verification constraints

• HasI1Element(mask)
• HasIndexOrNonI1IntegerElement(offsets)
• SameElementType(value, view, passthrough, result)
• SameShape(offsets, mask, value)
• SameType(value, passthrough, result)

Examples

%old = vector.atomic.rmw.mask<addf> %v, %view[%row, %col][%offsets], %mask, %passthrough {ordering = relaxed, scope = device} : vector<4xf32>, view<[%m]x[%n]xf32, %layout>, vector<4xindex>, vector<4xi1>, vector<4xf32>