vector.dot4f8

← vector dialect

Treat each i32 source lane as a little-endian pack of four 8-bit floating-point fields, decode fields according to the fp8/bf8 template, and add the four-product fused sum into the matching f32 accumulator lane. The fp8 spelling names the E4M3 primitive float format and bf8 names the E5M2 primitive float format. This is a packed-storage register dot matching AMDGPU dot4.f32.fp8/bf8 families without requiring unpacked f8 vector source lanes.

Operation contract

Property	Value
Semantic phase	executable
Traits	Pure

Signature

Kind	Name	Type	Cardinality	Description
Operand	lhs	vector	required	i32 lanes holding packed lhs 8-bit float fields.
Operand	rhs	vector	required	i32 lanes holding packed rhs 8-bit float fields.
Operand	acc	vector	required	f32 accumulator lanes updated by each packed four-lane dot product.
Result	result	vector	required	Updated f32 accumulator lanes.
Attribute	kind	enum FloatDot4F8Kind	required	—

Verification constraints

• HasI32Element(lhs)
• HasF32Element(acc)
• SameType(lhs, rhs)
• SameType(acc, result)
• SameShape(lhs, acc)

Examples

%r = vector.dot4f8<fp8bf8> %lhs, %rhs, %acc : vector<4xi32>, vector<4xf32>

%r = vector.dot4f8<bf8fp8> %lhs, %rhs, %acc : vector<[%N]xi32>, vector<[%N]xf32>