vector.store.compress
← vector dialect
Rank-1 masked compress store to consecutive view elements. Active lanes write densely in increasing lane order; inactive lanes do not produce memory elements.
Operation contract
| Property |
Value |
| Semantic phase |
— |
| Interfaces |
MemoryAccess |
| Memory effects |
write view |
Signature
| Kind |
Name |
Type |
Cardinality |
Description |
| Operand |
value |
vector |
required |
Rank-1 vector value to store. |
| Operand |
view |
view |
required |
Typed destination view. |
| Operand |
mask |
vector |
required |
i1 rank-1 vector mask selecting stored lanes. |
| Operand |
indices |
index |
variadic |
Dynamic logical origin indices. |
| Attribute |
cache_scope |
enum CacheScope |
optional |
Optional cache/coherency scope required by target lowering. |
| Attribute |
cache_temporal |
enum CacheTemporal |
optional |
Optional temporal cache policy required by target lowering. |
| Attribute |
static_indices |
i64_array |
required |
Static logical origin indices with INT64_MIN sentinels for dynamics. |
Verification constraints
HasRankOneVector(value)
HasI1Element(mask)
SameElementType(value, view)
SameShape(mask, value)
Examples
vector.store.compress %v, %view[%row, %col], %mask : vector<4xf32>, view<[%m]x[%n]xf32, %layout>, vector<4xi1>