Welcome to the Omniperf Documentation!

Table of Contents

• Introduction
  • What is Omniperf
  • Features
  • Compatible SoCs
• High Level Design
• Deployment
  • Client-side Installation
    • Execution using modulefiles
    • Execution without modulefiles
    • rocProf
  • Server-side Setup
    • Install MongoDB Utils
    • Persistent Storage
    • Build and Launch
    • Setup Grafana Instance
    • MongoDB Datasource Configuration
    • Omniperf Dashboard Import
    • Using your dashboard
• Getting Started
  • Quickstart
  • Usage
    • Modes
    • Global Options
  • Basic Operations
• Profile Mode
  • Workload Compilation
  • Omniperf Profiling
    • Features
    • Demo
    • Filtering
      • Hardware Component Filtering
      • Kernel Filtering
      • Dispatch Filtering
    • Standalone Roofline
      • Roofline Only
• Analyze Mode
  • CLI Analysis
    • Features
    • Demo
    • More options
  • GUI Analysis
    • Web-based GUI
      • Features
      • Usage
    • Grafana-based GUI
      • Features
      • Grafana GUI Import
      • Omniperf Panels
• AMD Instinct™ MI Series Accelerator Performance Model
  • Compute Unit (CU)
    • Pipeline Descriptions
      • Vector Arithmetic Logic Unit (VALU)
      • Scalar Arithmetic Logic Unit (SALU)
      • Local Data Share (LDS)
      • Branch
      • Scheduler
      • Matrix Fused Multiply-Add (MFMA)
      • Non-pipeline resources
    • Pipeline Metrics
      • Wavefront
      • Instruction Mix
      • Compute Pipeline
    • Local Data Share (LDS)
      • LDS Speed-of-Light
      • Statistics
    • Vector L1 Cache (vL1D)
      • vL1D Speed-of-Light
      • Address Processing Unit or Texture Addresser (TA)
      • L1 Unified Translation Cache (UTCL1)
      • Vector L1 Cache RAM (TC)
      • Vector L1 Data-Return Path or Texture Data (TD)
  • L2 Cache (TCC)
    • L2 Speed-of-Light
    • L2 Cache Accesses
    • L2-Fabric transactions
      • Request flow
      • Metrics
      • Detailed Transaction Metrics
    • L2-Fabric Interface Stalls
  • Shader Engine (SE)
    • Scalar L1 Data Cache (sL1D)
      • Scalar L1D Speed-of-Light
      • Scalar L1D Cache Accesses
      • sL1D ↔ L2 Interface
    • L1 Instruction Cache (L1I)
      • L1I Speed-of-Light
      • L1I Cache Accesses
      • L1I - L2 Interface
    • Workgroup manager (SPI)
      • Workgroup Manager Utilizations
      • Workgroup Manager - Resource Allocation
  • Command Processor (CP)
    • Command Processor Fetcher (CPF) Metrics
    • Command Processor Packet Processor (CPC) Metrics
  • System Speed-of-Light
  • References
  • Disclaimer
• Definitions
  • Miscellaneous
  • Normalization units
  • Memory Spaces
  • Memory Type
• Profiling with Omniperf by Example
  • VALU Arithmetic Instruction Mix
    • Design note
    • Instruction mix
  • Infinity-Fabric™ transactions
    • Experiment #1 - Coarse-grained, accelerator-local HBM reads
    • Experiment #2 - Fine-grained, accelerator-local HBM reads
    • Experiment #3 - Fine-grained, remote-accelerator HBM reads
    • Experiment #4 - Fine-grained, CPU-DRAM reads
    • Experiment #5 - Coarse-grained, CPU-DRAM reads
    • Experiment #6 - Fine-grained, CPU-DRAM writes
    • Experiment #7 - Fine-grained, CPU-DRAM atomicAdd
  • Vector memory operation counting
    • Global / Generic (FLAT)
      • Design note
      • Global Write
      • Generic Write to LDS
      • Global read
      • Generic read from global memory
      • Global atomic
      • Generic, mixed atomic
    • Spill/Scratch (BUFFER)
  • Instructions-per-cycle and Utilizations example
    • Design note
    • VALU Utilization and IPC
    • Exploring “Issued” IPC via MFMA operations
    • “Internal” instructions and IPC
    • SALU Utilization
    • VALU Active Threads
  • LDS Examples
    • LDS Bandwidth
    • Bank Conflicts
  • Occupancy Limiters Example
    • Design note
    • VGPR Limited
    • LDS Limited
    • SGPR Limited
• FAQ